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cmos 8-bit single chip microcomputer description the cxp822p24 is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, capture timer counter, fluorescent display tube controller/driver, remote control reception circuit, ctl duty detection circuit, 14-bit pwm output and high- speed output circuit besides the basic configurations of 8-bit cpu, prom, ram, and i/o port. the cxp822p24 also provides sleep/stop function that enables lower power consumption. cxp822p24 is the prom-incorporated version of the cxp82224 with built-in mask rom. this provides the additional feature of being able to write directly into the program. thus, it is most suitable for evaluation use during system development and for small- quantity producton. features wide-range instruction system (213 instructions) to cover various types of data. ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 400ns at 10mhz operation 122s at 32khz operation incorporated prom capacity 24k bytes incorporated ram capacity 704 bytes (including fluorescent display area) peripheral functions ?a/d converter 8-bit, 8-channel, successive approximation method (conversion time of 32s/10mhz) ?serial interface sio with 8-bit, 8-stage fifo incorporated for data use (auto transfer for 1 to 8 bytes), 1 channel 8-bit standard sio, 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer 16-bit capture timer/counter, 32khz timer/counter ?fluorescent display tube controller/driver maximum of 384 segment display possible 1 to 16-digit dynamic display dimmer function high voltage drive output (40v) incorporated pull-down resistor hardware key scan function maximum of 16 8 key matrix compatible ?remote control reception circuit incorporated noise elimination circuit incorporated 8-bit, 6-stage fifo for measurement data ?pwm output circuit 14 bits, 1 channel ?ctl duty detection circuit ?high-speed output circuit precision of 800ns at 10mhz, 4 outputs. interruption 19 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp ?1 e93242a78-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp822p24 100 pin qfp (plastic) structure silicon gate cmos ic
?2 cxp822p24 a/d converter fdp controller/ driver 14 bit pwm generator ctl duty det remocon serial interface unit 1 8 bit timer/counter 0 8 bit timer 1 16 bit capture timer/counter 2 ram 80 bytes fifo serial interface unit 0 fifo interrupt controller spc700 cpu core prom 24k bytes clock gen./ system control ram 704 bytes 2 2 2 2 2 prescaler/ time base timer 32khz timer/counter realtime pulse generator ch0 ch1 2 8 8 8 24 av ref av ss pe0/ec0/int0 pe1/ec1/int1 pe2/int2 pe3/int3/nmi v ss v dd rst xtal extal tx tex pg0/rto0 to pg3/rto3 port a port b port c port d port e port f port g port h port i 4 8 8 8 8 8 8 8 6 2 8 pa0/an0 to pa7/an7 t0 to t7 t8/s31 to t15/s24 pd0/s0 to pi7/s23 vfdp pe6/pwm pe5/ctl pe7/ddo pe4/rmc pb1/cso pb3/si0 pb4/so0 pb2/sck0 pb6/si1 pb7/so1 pb5/sck1 pe0/ec0 pe7/to pb0/cint pe1/ec1 pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe5 pe6 to pe7 pf0 to pf7 pg0 to pg7 ph0 to ph7 pi0 to pi7 block diagram
?3 cxp822p24 pe1/ec1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/ctl pe6/pwm pe7/to/ddo/adj pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0/kr0 pc1/kr1 pc2/kr2 pc3/kr3 pc4/kr4 pc5/kr5 pc6/kr6 pc7/kr7 ph0 ph1 ph2 ph3 ph4 ph5 ph6 t7 t8/s31 t9/s30 t10/s29 t14/s25 t15/s24 p17/s23 p16/s22 p15/s21 p14/s20 p13/s19 p12/s18 p10/s16 pf7/s15 pf6/s14 pf5/s13 pf4/s12 pf3/s11 pf2/s10 pf1/s9 pf0/s8 pd7/s7 pd6/s6 pd5/s5 pd4/s4 pd3/s3 ph7 pa0/an0 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 rst extal xtal v ss tx tex pa6/an6 pa7/an7 av ref av ss pd0/s0 pd1/s1 pd2/s2 pg1/rto1 pe0/ec0/int0 pg7 pg5 pg4 pg3/rto3 pg2/rto2 pg0/rto0 v ss v pp v dd v fdp t0 t1 t2 t3 t4 t5 t6 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 p11/s17 t12/s27 t13/s26 t11/s28 pg6 note) v pp (pin 90) must be connected to v dd. pin assignment (top view)
cxp822p24 pin description ?4 (port a) 8-bit i/o port. i/o can be set in a unit of single bit . (8 pins) (port b) 8-bit i/o port. i/o for lower 7bits can be set in a unit of single bits. uppermost bit (pb7) is for output only. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma sync current. (port d) 8-bit output port. (8 pins) (port e) 8-bit port. lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) (port f) 8-bit output port. (8 pins) (port g) 8-bit i/o port. i/o can be set in a unit of single bits. data for the lower 4 bits are gated with the contents of rto or or-gate output. (8 pins) analog inputs to a/d converter. (8 pins) capture input to 16-bit timer/counter. chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). serves as key return inputs when operating key scan with fdp segment signal. fdp segment signal outputs. inputs for external interruption request. (4 pins) remote control reception circuit input. input for ctl duty direction circuit. 14-bit pwm output. output for the 16-bit timer/counter rectangular waves, ctu duty detection, and 32khz oscillation frequuency demultiplication. outputs for real-time pulse generator (rtg). functions as high-precision, real-time pulse output port. (4 pins) symbol i/o functions pa0/an0 to pa7/an7 pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0/kr0 to pc7/kr7 pd0/s0 to pd7/s7 pe0/int0/ec0 pe1/int1/ec1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/ctl pe6/pwm pe7/to/ddo/ adj pf0/s8 to pf7/s15 pg0/pto0 to pg3/rto3 pg4 to pg7 i/o/ analog input i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input output/output i/o/input output/output input/input/input input/input/input input/input input/input/input input/input input/input output/output output/output/ output/output output/output i/o/output i/o external event inputs for timer/counter. (2 pins) non-maskable interruption request input. fdp segment signal outputs.
?5 cxp822p24 (port h) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port i) 8-bit output ports. fdp segment signal outputs. (8 bits) outputs for fdp timing (digit) signals/sagment signals. fdp timing signal outputs. fdp voltage supply when incorporated resistor is set by mask option. crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. crystal connectors for 32khz timer/counter clock oscillation. set 32khz crystal oscillator between tex and tx. for usage as event input, attach clock source to tex, and open tx. low-level active, system reset. reference voltage input for a/d converter. a/d converter gnd. vcc supply. vcc supply for incorporated prom writing. connect to v dd during normal operation. gnd. symbol i/o functions ph0 to ph7 pi0/s16 to pi7/s23 t8/s31 to t15/s24 t0 to t7 v fdp extal xtal tex tx rst av ref av ss v dd vpp v ss i/o output/output output/output output input output input output input input
?6 cxp822p24 when reset pin circuit format input/output circuit formats for pins ip rd (port b) data bus port b direction port b output selection "0" when reset sck in schmitt input port b data "0" when reset sck out output enable hi-z hi-z hi-z pb0/cint pb1/cs0 pb3/si0 pb6/si1 pb2/sck0 pb5/sck1 port b port b 2 pins port a ip input protection circuit rd (port a) data bus port a direction port a data "0" when reset port a input selection "0" when reset a/d converter input multiplexer ip rd (port b) data bus port b direction port b data "0" when reset cint cs0 si0 si1 schmitt input pa0/an0 to pa7/an7 8 pins 4 pins
?7 cxp822p24 when reset pin circuit format ip rd (port b) data bus port b direction port b output selection "0" when reset port b data "0" when reset so output enable port b port c port e 1 pin high level hi-z hi-z pb4/so0 pb7/so1 1 pin 8 pins hi-z pc0/kr0 to pc7/kr7 6 pins pe0/ec0/int0 pe1/ec1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/ctl port b ip rd (port c) data bus port c direction port c data "0" when reset key input signal * high current drive of 12ma possible * rd (port e) ip ec0/int0 ec1/int1 int2 int3/nmi rmc ctl data bus schmitt input rd (port b) data bus port b output selection "1" when reset port b data "1" when reset so output enable internal reset signal * * pull-up transistor approx. 200k w
?8 cxp822p24 when reset pin circuit format ip rd (port g) data bus port g direction port g data "0" when reset rto data "0" when reset rd (port e) data bus port e output selection "1" when reset port e data "0" when reset * * adj signal is a frequency demultiplication output for 32khz oscillation frequency adjustment. adj2 can be used for buzzer output. port e output selection port e output selection 0 1 2 3 mpx to ddo adj16k adj2k output enable * "00" when reset rd (port e) data bus port e output selection "1" when reset port e data "0" when reset pwm port e 1 pin high level hi-z pe6/pwm pe7/to/ ddo/adj port g 1 pin 4 pins high level pg0/rto0 to pg3/rto3 port e
?9 cxp822p24 v fdp * rd (port d, f, or i) data bus "0" when reset port d, f, or i data ("0" when reset) segment output data output selection control signal * high voltage drive transistor mask option pull-down resistor op 24 pins hi-z or low level (when pd resistance is added) oscillation when reset pd0/s0 to pd7/s7 pf0/s8 to pf7/s15 pi0/s16 to pi7/s23 t15/s24 to t8/s31 t0 to t7 16 pins 2 pins extal xtal hi-z or low level (when pd resistance is added) port d port g port h port f port i pin circuit format v fdp * ("0" when reset) segment output data output selection control signal * high voltage drive transistor mask option pull-down resistor op ip ip extal xtal * diagram shows circuit composition during oscillation. * feedback resistor is removed during stop. hi-z 12 pins pg4 to pg7 ph0 to ph7 ip rd (port g or port h) data bus port g or port h direction port g or port h data "0" when reset
?10 cxp822p24 2 pins oscillation tex tx ip ip tex tx * when the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and tex and tx become "low" level and "high" level respectively. * diagram shows circuit composition during oscillation. 1 pin low level rst mask option ip schmitt input pull-up resistor op when reset pin circuit format
?11 cxp822p24 * 1 v in and v out must not exceed v dd + 0.3v. * 2 specifies output current of general-purpose l/o ports. * 3 the high current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsl. supply voltage input voltage output voltage display output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd vpp av ss v in v out v od i oh i odh1 i odh2 i oh i odh i ol i olc i ol topr tstg p d incorporated prom as p channel transistor is open drain, v dd is reference. all pins excluding display outputs * 2 (value per pin) display outputs s0 to s23 (value per pin) display outputs t0 to t7, and t8/s31 to t15/s24 (value per pin) total for all pins excluding display outputs total for all display outputs port 1 high current port 1 * 3 total for all output pins item symbol rating unit remarks absolute maximum ratings (vss = 0v reference) ?.3 to +7.0 ?.3 to +13.0 ?.3 to +0.3 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 v dd ?40 to v dd + 0.3 ? ?5 ?5 ?0 ?00 15 20 100 ?0 to +75 ?5 to +150 600 v v v v v v ma ma ma ma ma ma ma ma ? ? mw
?12 cxp822p24 high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v ? v item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 vpp v ih v ihs v ihex v il v ils v ilex topr high-speed mode guaranteed operation range low-speed mode guaranteed operation range guaranteed operation range with tex clock guaranteed data hold range during stop * 4 * 1 hysteresis input * 2 extal * 3 * 1 hysteresis input * 2 extal * 3 v dd * 1 value for each pin of normal input ports (pa, pb3, pb4, pb6, pc, pg, ph). * 2 value of the following pins: rst, cint, cs0, sck0, sck1, ec0/int0, ec1/int1 , int2, int3/mti, rmc, ctl. * 3 specifies only during external clock input. * 4 vpp and v dd should be set to the same voltage. recommended operating conditions (vss = 0v reference) vpp = v dd
?13 cxp822p24 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ? ?0 60 v v v v v ? ? ? ? ? ma ma ? k ? ma ? ma ? ? pf pc extal tex rst item symbol pins conditions min. v dd i dd1 i oh i lol i dd2 i dds1 i dds2 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 ?0 270 10 40 1000 8 30 30 20 max. unit dc characteristics electrical characteristics (ta = ?0 to +75?, vss = 0v reference) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) power supply current * input capacity v dd = 5.5v, v il = 0.4v v dd = 4.5v, v oh = v dd ?2.5v v dd = 5.5v v ol = v dd ?35v v fdp = v dd ?35v high-speed mode operation (1/2 frequency demultiplier clock) stop mode v dd = 5.5v, termination of 10mhz and 32khz crystal oscillation clock 1mhz 0v for all pins excluding measured pins display output current i iz i/o leakage current open drain output leakage current (p-ch tr in off state) s0 to s23 s24/t15 to s31/t8 t0 to t7 s24/t15 to s31/t8 t0 to t7 r l v dd = 5v v fdp = v dd ?35v v dd = 5.5v v i = 0, 5.5v pull-down resistance s24/t15 to s31/t8 t0 to t7 pa to pc, pe, pg, ph 100 20 400 1.2 9 10 pa, pb, pc,pe6, pe7, pg, ph pins other than s0 to s31, t0 to t7, pb7, pe6, av ref , av ss , v fdp , v dd , v ss sleep mode * when all pins are open.
?14 cxp822p24 * 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") extal t xh t xl t cf t cr 0.4v v dd ?0.4v 1/fc aaaa a aa a aaaa external clock extal xtal 74hc04 aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input pulse width event count input rise time, fall time f c t xl t xh t cr t cf t eh t el t er t ef f c t tl t th t tr t tf xtal extal extal extal ec0, ec1 ec0, ec1 tex tx tex tex mhz ns ns ns ms khz ? ms item symbol pin conditions unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock application condition) fig. 3 fig. 3 typ. 32.768 min. 1 37.5 t sys + 50 * 1 10 max. 10 200 20 20 (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing fig. 2. clock applied conditions
?15 cxp822p24 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck0 output mode, so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss=0v reference) item cs0 ? sck0 delay time cs0 - ? sck0 float delay time cs0 ? so0 delay time cs0 - ? so0 float delay time cs0 high level width sck0 cycle time sck0 high, low level width si0 input set-up time (for sck0 - ) si0 input hold time (for sck0 - ) sck0 ? so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit condition tex ec0 ec1 t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing
cxp822p24 fig. 4. serial transfer ch0 timing cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 ?16
?17 cxp822p24 serial transfer (ch1) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. condition sck1 cycle time sck1 high, low level width si1 input set-up time (for sck1 - ) si1 input hold time (for sck1 - ) sck1 ? so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 1000 16000/fc 400 8000/fc ?50 100 200 200 100 200 100 unit ns ns ns ns ns ns ns ns ns ns note) the load condition for the sck1 output mode, so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd
?18 cxp822p24 (3) a/d converter characteristics v zt * 1 v ft * 2 t conv t samp v ref v ian i ref i refs ta = 25c v dd = av dd = 5.0v v dd = avss = 0v operation mode sleep mode stop mode 32khz operation mode av ref ?0 4930 160/f adc * 3 12/f adc * 3 v dd ?0.5 0 item symbol pin condition min. typ. max. unit bits resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time reference input voltage analog input voltage av ref current (ta = 10 to +75c, v dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = avss = 0v reference) 8 ? 150 5120 v dd av ref 1.0 10 70 5050 0.6 lsb mv mv ? ? v v ma ? analog input linearity error 00 h 01 h fe h ff h digital conversion value v zt v ft fig. 6. definitions of a/d converter terms av ref an0 to an7 * 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to adc operation clock selection (adcs: bit 6 of address 00f9 h ). during ps2 selection, f adc = fc/2 during ps1 selection, f adc = fc
?19 cxp822p24 external interruption high, low level width reset input low level width int0 int1 int2 nmi/int3 rst 1 8/fc ? ? item symbol pin condition min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) 0.8v dd 0.2v dd t ih t il int0 int1 int2 nmi/int3 (nmi specifies only for the falling edge) t il t ih fig. 7. interruption input timing t rsl 0.2v dd rst fig. 8. rst input timing 0.2v dd 0.8v dd t cth t ctl ctl fig. 9. other timing clk input high, low level width t cth t ctl ctl item symbol pin condition min. max. unit ns (5) others (ta = ?0 to +75?, v dd = 4.5 to 5.0v, v ss = 0v reference) t sys = 2000/fc t sys + 200
?20 cxp822p24 appendix fig. 10. recommended oscillation circuit aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd (i) main clock aaaaa a aaa a aaaaa extal xtal c 2 rd (ii) main clock aaaa aaa a aaaa tex tx c 1 c 2 rd (iii) sub clock c 1 manufacturer murata mfg co., ltd river eletec corporation kinseki ltd. csa4.19mg csa8.00mtz csa10.0mtz cst4.19mgw * cst8.00mtw * cst10.0mtw * hc-49/u03 hc-49/u (-s) p3 model fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 32.768khz 30 15 27 30 30 15 27 39 0 0 0 330k c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (ii) (i) (iii) those marked with an asterisk ( * ) signify types with built-in ground capacitance (c 1 , c 2 ). optional item mask product CXP822P24Q-1- package rom capacitance reset pin pull-up resistor high voltage drive pin pull-up resistor 100-pin plastic qfp 20k bytes/24k bytes existent/non-existent existent/non-existent 100-pin plastic qfp prom 24k bytes existant non existent (s0/pd0 to s23/pf7) existent (t0 to t15/s24) selection guide
?21 cxp822p24 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g

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